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charge pump regulator for color tft panels adm8839 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 3 voltages (+5 v, +15 v, ?15 v) from a single 3 v supply power efficiency optimized for use with tft in mobile phones low quiescent current low shutdown current (<5 a) shutdown function option to use external ldo applications hand-held instruments tft lcd panels cellular phones functional block diagram oscillator control logic timing generator shutdown control discharge voltage inverter voltage tripler ldo voltage regulator voltage doubler c1+ c1? ldo_in vout +5vout c2+ c2? c3+ c3? +15vout c4+ c4? ?15vout ?15v +15v +5v gnd shdn ldo_on/off v cc double triple c5, 2.2f c1, 2.2f c6, 2.2f c7, 2.2f c8, 0.22f c9, 0.22f c2, 0.22f c3, 0.22f c4, 0.22f adm8839 +5vin 03075-001 figure 1. general description the adm8839 is a charge pump regulator used for color thin film transistor (tft) liquid crystal displays (lcds). using charge pump technology, the device can be used to generate three voltages (+5 v 2%, +15 v, ?15 v) from a single 3 v supply. these voltages are then used to provide supplies for the lcd controller (5 v) and the gate drives for the transistors in the panel (+15 v and ?15 v). only a few external capacitors are needed for the charge pumps. an efficient low dropout (ldo) voltage regulator ensures that the power efficiency is high, and provides a low ripple 5 v output. this ldo can be shut down and an external ldo can be used to regulate the 5 v doubler output and drive the input to the charge pump section that generates the +15 v and ?15 v outputs, if required by the user. the adm8839 has a power save shutdown feature. the 5 v output consumes the most power, so power efficiency is also maximized on this output with an oscillator-enabling scheme (green idle?). this effectively senses the load current that is flowing and turns on the charge pump only when charge needs to be delivered to the 5 v pump doubler output. the adm8839 is fabricated using cmos technology for minimal power consumption. the part is packaged in a 20-lead lfcsp (lead frame chip scale package).
adm8839 rev. c | page 2 of 12 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 3 absolute maximum ratings............................................................ 4 thermal characteristics .............................................................. 4 esd caution...................................................................................4 pin configuration and function descriptions..............................5 typical performance characteristics ..............................................6 theory of operation .........................................................................8 power sequencing .........................................................................8 transient response .......................................................................8 boosting the current drive of the 15 v supply .....................8 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 10 revision history 7 /06rev. b to rev. c updated format..................................................................universal changes to table 1............................................................................ 3 changes to table 5............................................................................ 5 changes to ordering guide .......................................................... 10 updated outline dimension......................................................... 10 7/05rev. a to rev. b updated ordering guide .................................................................3 2/03rev. 0 to rev. a changed specifications.....................................................................2 updated outline dimensions..........................................................8
adm8839 rev. c | page 3 of 12 specifications v cc = 3 v (+40%/?10%); t a = ?40c to +85c; c1, c5, c6, c7 = 2.2 f; c2, c3, c4, c8, c9 = 0.22 f; unless otherwise noted. table 1. parameter test conditions min typ max unit input voltage, v cc 2.7 4.2 v supply current, i cc unloaded 250 500 a shutdown mode, t a = 25c 5 a +5 v output output voltage i l = 10 a to 20 ma 4.9 5.0 5.1 v output current 5 20 ma output ripple 8 ma load 10 mv p-p transient response i l stepped from 10 a to 8 ma 5 s +15 v output output voltage i l = 1 a to 150 a 14.0 15.0 16.0 v output current 1 150 a output ripple i l = 100 a 50 mv p-p ?15 v output output voltage i l = ?1 a to ?150 a ?16.0 ?15.0 ?14.0 v output current ?150 ?1 a output ripple i l = ?100 a 50 mv p-p power efficiency r5 v out load = 5 ma, 15 v load = 150 a, v cc = 3.0 v 82 % charge pump frequency 60 100 140 khz control pins, shdn input voltage, v shdn shdn low = shutdown mode 0.3 v cc v shdn high = normal mode 0.7 v cc v digital input current 1 a digital input capacitance 1 10 pf ldo_on/off input voltage low = external ldo 0.3 v cc v high = internal ldo 0.7 v cc v digital input current 1 a digital input capacitance 1 10 pf 1 guaranteed by design. no t 100% production tested. timing specifications v cc = 3 v, t a = 25c; c1, c5, c6, c7 = 2.2 f; c2, c3, c4, c8, c9 = 0.22 f. table 2. parameter test conditions/comments min typ max unit power-up sequence +5 v rise time, t r5v 10% to 90%, see figure 14 250 s +15 v rise time, t r15v 10% to 90%, see figure 14 3 ms ?15 v fall time, t fm15v 90% to 10%, see figure 14 3 ms delay between ?15 v fall and +15 v, t delay see figure 14 600 s power-down sequence +5 v fall time, t f5v 90% to 10%, see figure 14 35 ms +15 v fall time, t f15v 90% to 10%, see figure 14 10 ms ?15 v rise time, t rm15v 10% to 90%, see figure 14 20 ms
adm8839 rev. c | page 4 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating supply voltage ?0.3 v to +6.0 v input voltage on digital inputs ?0.3 v to +6.0 v output short-circuit duration to gnd 10 sec output voltage +5 v output 0 v to 7.0 v C15 v output ?17 v to +0.3 v +15 v output ?0.3 v to +17 v operating temperature range ?40c to +85c power dissipation 50 mw storage temperature range ?65c to +150c esd class i stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja unit 20-lead lfcsp_vq 31c c/w esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adm8839 rev. c | page 5 of 12 pin configuration and fu nction descriptions v cc 1 vout 2 ldo_in 3 11 c3? ldo_on/off 6 shdn 7 v cc 8 gnd 9 +15vout 10 +5vout 4 +5vin 5 17 ?15vout 16 c4+ pin 1 indicator top view adm8839 12 c3+ 13 c2? 14 c2+ 15 c4? 18 gnd 19 c1? 20 c1+ 0 3075-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v cc positive supply voltage input. connect this pin to the 3 v supply with a 2.2 f decoupling capacitor. must be electrically tied together with pin 8 by a pcb trace. 2 vout voltage doubler output. this is derived by doubling the 3 v supply. a 2.2 f capacitor to ground is required on this pin. 3 ldo_in voltage regulator input. the user can by pass this circuit by using the ldo_on/ off pin. 4 +5vout 5 v output. this is derived by doubling and regulating the 3 v supply. a 2.2 f capacitor to ground is required on this pin to stabilize the regulator. 5 +5vin 5 v input. this is the input to the vo ltage tripler and inverter charge pump circuits. 6 ldo_on/ off control logic input. 3 v cmos logic. a logic high selects the internal ldo for regulation of the 5 v voltage doubler output. a logic low isolates th e internal ldo from the rest of the charge pump circuits. this allows the use of an external ldo to regulate the 5 v voltage double r output. the output of this ldo is then fed back into the voltage tripler and inverter circuits of the adm8839. 7 shdn digital input. 3 v cmos logic. active low shutdown control. this shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 v. 8 v cc connect this pin to v cc . must be electrically tied with pin 1 by a pcb trace. 9 gnd connect this pin to gnd. must be electrically tied with pin 18 by a pcb trace. 10 +15vout 15 v output. this is derived by tripling the 5 v regulated output. a 0.22 f capacitor is required on this pin. 11, 12 c3?, c3+ external capacitor c3 is connected between these pins. a 0.22 f capacitor is recommended. 13, 14 c2?, c2+ external capacitor c2 is connected between these pins. a 0.22 f capacitor is recommended. 15, 16 c4?, c4+ external capacitor c4 is connected between these pins. a 0.22 f capacitor is recommended. 17 ?15vout ?15 v output. this is derived by tripling and inverting the 5 v regulated output. a 0.22 f capacitor is required on this pin. 18 gnd device ground. must be electrically tied with pin 9 by a pcb trace. 19, 20 c1?, c1+ external capacitor c1 is connected between these pins. a 2.2 f capacitor is recommended.
adm8839 rev. c | page 6 of 12 typical performance characteristics supply voltage (v) ldo o/p voltage (v) 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 3.1 9 .3 5.3 7. 2 2.9 3.3 3.7 4.1 4.2 device at ?40c device at +85c device at +25c 03075-003 figure 3. ldo o/p voltage variation over temperature and supply i load (ma) ldo o/p voltage (v) 4.995 5.000 5.005 5.010 5.015 5.020 2 04 6 1357 8 03075-004 figure 4. ldo o/p voltage vs. load current i load (a) +15v/?15v power efficiency (%) 30 40 50 60 70 80 90 100 30 0 01 07 05 0 19 20 40 60 80 0 0 3075-005 figure 5. +15 v/?15 v power efficiency vs. load current load current (ma) ldo power efficiency (%) 75 76 77 78 79 80 81 84 82 38 7 5 12 4 6 83 03075-006 figure 6. ldo power efficiency vs. load current, v cc = 3 v supp ly voltag e (v) supply current (a) 150 200 250 300 350 400 3.1 9 .3 5.3 7. 2 2.9 3.3 3.7 4.1 4.2 03075-007 figure 7. supply current vs. supply voltage i load (a) output voltage (v) 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 15.0 15.1 50 0 100 150 200 ?15v at 25c +15v at 25c 0 3075-008 figure 8. +15 v/?15 v output voltage vs. load current, typical configuration
adm8839 rev. c | page 7 of 12 +15v output ?15v output 5vout 03075-009 figure 9. +15 v and ?15 v outputs at power-up v out ripple (doubler output ripple) ldo output ripple v cc ripple 03075-010 figure 10. output ripple on ldo (5 v output) load disable 5v output 03075-011 figure 11. 5 v output transient response, load disconnected load enable 5v output 03075-012 figure 12. output transient response for maximum load current +15v output ?15v output 5vout 03075-013 figure 13. +15 v and ?15 v outputs at power-down
adm8839 rev. c | page 8 of 12 theory of operation power sequencing for the tft panel to power up correctly, the gate drive supplies must be sequenced such that the ?15 v supply is up before the +15 v supply. the adm8839 controls this sequence. when the device is turned on (a logic high on shdn ), the adm8839 allows the ?15 v output to ramp immediately but holds off the +15 v output. it continues to do this until the negative output has reached ?3 v. at this point, the positive output is enabled and allowed to ramp to +15 v. this sequence is highlighted in figure 14 . v cc shdn +5v +15v ?15v t rm15v t fm15v t delay 10% 10% 10% 90% 90% 90% t f15v t r15v t f5v t r5v ?3v 03075-014 figure 14. power sequence transient response the adm8839 features extremely fast transient response, making it very suitable for fast image updates on tft lcd panels. this means that even under changing load conditions, there is still very effective regulation of the 5 v output. figure 11 and figure 12 show how the 5 v output responds when a maximum load is dynamically connected and disconnected. note that the output settles within 5 s to less than 1% of the output level. boosting the current drive of the 15 v supply the adm8839 15 v output can deliver 150 a of current in the typical configuration, as shown in figure 15 . it is also possible to draw 100 a from the +15 v output and 200 a from the ?15 v output, or vice versa. it is possible to draw a maximum of only 300 a combined from the +15 v and the ?15 v outputs at any time (see figure 16 ). in this configuration, +5vout (pin 4) is connected to +5vin (pin 5), as shown in the functional block diagram (see figure 1 ). oscillator control logic timing generator shutdown control discharge voltage inverter voltage tripler ldo voltage regulator voltage doubler c1+ c1? ldo_in vout +5vout c2+ c2? c3+ c3? +15vout c4+ c4? ?15vout ?15v +15v +5v gnd shdn ldo_on/off v cc double triple c5, 2.2f c1, 2.2f c6, 2.2f c7, 2.2f c8, 0.22f c9, 0.22f c2, 0.22f c3, 0.22f c4, 0.22f adm8839 +5vin 03075-015 figure 15. typical configuration i load (a) output voltage (v) 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 15.0 15.1 50 0 100 150 200 ?15v at 25c +15v at 25c 03075-016 figure 16. +15 v/?15 v output voltage vs. load current, typical configuration
adm8839 rev. c | page 9 of 12 it is possible to configure the adm8839 to supply up to 400 a on the 15 v outputs by changing its configuration slightly, as shown in figure 17 . oscillator control logic timing generator shutdown control discharge voltage tripler ldo voltage regulator voltage doubler current boost configuration connection c1+ c1? ldo_in vout +5vout c2+ c2? c3+ c3? +15vout c4+ c4? ?15vout ?15v +15v +5v gnd shdn v cc double triple c5, 2.2f c1, 2.2f c7, 2.2f c8, 0.22f c9, 0.22f c2, 0.22f c3, 0.22f c4, 0.22f adm8839 +5vin c6, 2.2f ldo_on/off 03075-017 voltage inverter figure 17. current boost configuration the configuration in figure 17 can supply up to 400 a of current on both the +15 v and the ?15 v outputs. if the load on the 15 v does not draw any current, the voltage on the 15 v outputs can rise up to 16.5 v (see figure 18 ). in this configuration, vout (pin 2) is connected to +5vin (pin 5). 14.0 14.5 15.0 15.5 16.0 16.5 17.0 0 100 200 300 400 500 i load (a) output voltage (v) +15v at 25c ?15v at 25c 03075-018 figure 18. +15 v/?15 v output voltage vs. load current, current boost configuration
adm8839 rev. c | page 10 of 12 outline dimensions 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 19. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters ordering guide model temperature range ordering quantity package description package option adm8839acp ?40c to +85c 75 20-lead lfcsp_vq cp-20-1 adm8839acp-reel ?40c to +85c 5,000 20-lead lfcsp_vq cp-20-1 adm8839acp-reel7 ?40c to +85c 1,500 20-lead lfcsp_vq cp-20-1 adm8839acpz 1 ?40c to +85c 75 20-lead lfcsp_vq cp-20-1 adm8839acpz-reel 1 ?40c to +85c 5,000 20-lead lfcsp_vq cp-20-1 adm8839acpz-reel7 1 ?40c to +85c 1,500 20-lead lfcsp_vq cp-20-1 eval-adm8839eb evaluation board 1 z = pb-free part.
adm8839 rev. c | page 11 of 12 notes
adm8839 rev. c | page 12 of 12 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03075-0- 7 /06(c)

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